Friday, 24 June 2016



                                           
                     Hitachi Hardware Architecture

                         Hitachi USP/USP-V/USP-VM architecture is based on Hi-Star/Hierarchical Star/Universal Star Architecture.

USP/USP-V/USP-VM Architecture Components:

   USP V Haradware Architecture

 CHA – Channel Adapter or FED (Front End Director):

 o   CHA or FED Controls the Flow of data transfer between the hosts and the cache memory.
 o   CHA is a PCB board that contains the FEDs. FED is also called the CHA.
 o   FED ports can be FC/FICON. 2 ports are controlled by 1 processor. There can be 192 FC ports in USP/USP-V/USP-VM
 o   Data transfer speeds of up to 4Gbps/400MBPS.
 o   FC ports can be 16 or 32 ports per pair of CHA.
 o   FC ports support both long and short wavelengths to connect to hosts, arrays or switches.
 o   There can be 96 FICON ports in USP/USP-V/USP-VM
 o   Data transfer speeds of up to 2Gbps/200MBPS.
 o   FICON can have 8 or 16 ports per pair of FICON CHA. FICON ports can be short or long wavelengths.
 o   In USP100 – Max 2 FEDs In USP600 - Max of 4 or 6 FEDs In USP1100 – Max of 4 or 6 FEDs.

 DKA – Disk Adapter or BED (Back End Director):

 DKA or BED is a component of the DKC that Controls the flow of data transfer between the drive and cache memory.
• The Disk drives are connected to the DKA pairs by Fibre cables using an arbitrated loop FC-AL technology.
• Each DKA has 8 independent fibre back end paths controlled by 8 back-end directors (micro-processors).
• Max of 8 DKAs, hence 64 backend paths.
• Bandwidth of FC path = 2Gbps or 200MBPS
• In USP the number of Ports per DKA pair is 8 and each port is controlled by a Microprocessor (MP).
• The USP V can be configured with up to 8 BED pairs, providing up to 64 concurrent data transfers to and from the data drives.
• The USP VM is configured with 1 BED pair, which provides 8 concurrent data transfers to and from the data drives.
• In USP100- Max of 4 BEDs .
• In USP600 – Max of 4 BEDs.

Shared Memory:

• This is the memory that stores the configuration information and the information and status for controlling the Cache, Disk Drives and Logical devices, the path group arrays also reside in the SM.

• Size of the shared memory is determined by the

A. Total Cache Size
B. Number of LDEVs
C. Replication Software in use.

• Non-Volatile Shared Memory contains the cache directory and configuration information of the USP/USP-V/USP-VM
• SM is duplexes and each side of the duplex resides on the first two shared memory cards, which are in cluster 1 and 2.
• In the event of power failure the SM data is protected for up to 36 hours of battery back-up in USP-V and USP-VM.
• In the event of power failure the SM data on the USP is protected for up to 7 days.
• USP can be configured up to 3 GB from 2 cards or 6 GB from 4 cards.
• USP-V can be configured up to 32 GB of Shared memory.
• USP-VM can be configured up to 16 GB of shared Memory.

CM – Cache Memory :

• This is the memory that stores the user data in order to perform I/O ops asynchronously with the reading and writing to a disk drive.
• USP can be configured with up to 128GB of cache memory in increments of 4GB for USP100and 600 or 8GB for USP1100 and with 48hours of battery Backup.
• USP-V can be configured with up to 512GB of cache memory
• USP-VM can be configured with up to 128GB of cache memory.
• USP V and USP VM, both have a cache back up of power for 36 hours.
• The cache is divided into 2 equal areas called cache A and cache B on separate cards.
• Cache A is on Cluster 1 and Cache B is on Cluster 2
• All USP models place the read and write data in the cache.
• Write data is written to both the cache A and B, so the data is duplexes across both the logic and power boundaries.

        CSW Cache Switch This switch provides multiple data paths between CHA/DKA and cache memory.
       SVP Service processor Exclusive PC for performing all HW and SW maintenance functions.
       
·                   Power Supplies & Batteries

USP Features:

1. 100% data availability guarantee with no single point of failure.
2. Highly resilient, multi-path fibre channel architecture.
3. Fully redundant, hot swappable components .
4. Non-disruptive micro-code updates & Non-disruptive expansion.
5. Global Dynamic Hot Sparing .
6. Duplexed Cache with Battery Back-up .
7. Multiple point-to-point, data and control paths.
8. Supports all open systems and mainframes .
9. FC, FICON and ESCON connectivity
10. Fibre-Channel switched, arbitrated loop and point-to-point configurations.

 USP Components:

 The DKC consists of
v  DKC contains:
v  CHA/FEDs
v  DKA/BEDs
v  Cache Memories
v  Shared memories
v  CSWs
v  HDU boxes containing disk drives
v  Power supplies
v  Battery Box
v  The DKC unit is connected to a Service processor SVP, which is used to service the storage subsystem, monitor its running condition and analyze faults.

The DKU consists of

v  HDU - Each HDU box containing 64 disks.
v  Cooling Fans
v  AC power supply.



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